EPIC aims to develop a new generation of Forward-Error-Correction (FEC) codes to enable practical wireless Tb/s link technology—corresponding to a 10x–100x throughput improvement over the SoA. The EPIC concept and methodology is shaped by the key finding that routine progress in silicon technology in the next decade will not be sufficient to allow FEC implementations to break the Tb/s barrier; Tb/s FEC will require not only help from silicon technology but also major innovations in FEC algorithm design and implementation domains. A key EPIC objective is therefore to develop and utilize a disruptive FEC design framework that considers the FEC algorithm design and corresponding silicon implementation architectures in a unified fashion. Through such an integrated approach, EPIC aims to advance state-of-the-art FEC schemes (mainly Turbo, LDPC and Polar codes) to obtain the principal channel codes for beyond-5G (B5G) use-cases. Top-performing solutions developed under EPIC will be validated by virtual silicon tape-out implementations, thus providing first-in-class FEC blocks of wireless Tb/s technology. EPIC aims at utmost scientific excellence and leadership position in the FEC domain, contributing to European research and development, ensured by measurable and impactful scientific publications in leading journals/magazines in the FEC research area. EPIC will also contribute to the future of European research strength by organizing lectures and tutorials on FEC technology, targeting graduate students and post-graduate researchers. The EPIC concept comprises a technology roadmap, focusing on its SME partners, with the aim of converting fundamental research outcomes into market opportunities via technology IP generation and standardization contributions, ensured by IPR protection. The EPIC consortium, which includes the lead inventors and institutes in the FEC domain, dynamic SMEs, and impactful industry partners, is dedicated to successfully reaching these objectives.